INDUCTIVE INTERCONNECT WIDTH OPTIMIZATION For Low Power

The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the width of inductive interconnect. The optimum line width that minimizes the total transient power dissipation is determined in this paper. A closed form solution for the optimum width with an error of less than 6 % is presented. For a speci c set of line parameters and resistivities, the power is reduced by almost 80 % as compared to a minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined

Analog Integrated Circuits and Signal Processing, 41, 5–11, 2004 c ○ 2004 Kluwer Academic Publishers. Manufactured in The Netherlands. Resistive Power in CMOS Circuits

Abstract. Interconnect resistance dissipates a portion of the total transient power in CMOS circuits. Conduction losses increase with larger interconnect resistance. It is shown in this paper that these losses do not add to the total power dissipation of a CMOS circuit through I 2 R losses. Interconnect resistance can, however, increase the short-circuit power of both the driver and load gates

Transactions Briefs__________________________________________________________________ Shielding Effect of On-Chip Interconnect Inductance

Abstract—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17 % and area of 29 % are achieved for example circuits. An accurate model for a CMOS inverter and an load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9 % as compared to SPICE. Index Terms—CMOS, gate delay, interconnect modeling, on-chip inductance, propagation delay, interconnects, shielding effect. I

INTEGRATION, the VLSI journal 38 (2004) 205–225 Optimum wire sizing of RLC interconnect with repeaters

Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be considered in determining the optimum number and size of the repeaters driving a line. The optimum repeater system uses uniform repeater insertion in order to achieve the minimum propagation delay. A tradeoff exists, however, between the transient power dissipation and the minimum propagation delay in sizing long interconnects driven by the optimum repeater system. Optimizing the line width to achieve the minimum power delay product, however, can satisfy current high speed, low-power design objectives. A reduction in power of 65 % and delay of 97 % is achieved for an example repeater system. The Power-Delay-Area-Product (PDAP) criterion is introduced as an efficient technique to size the interconnect within a repeater system. A reduction in buffer area of 67 % and interconnect area of 46 % is achieved based on the PDAP. r 2004 Elsevier B.V. All rights reserved

Abstract INTEGRATION, the VLSI journal 40 (2007) 461–472 Wire shaping of RLC interconnects $

The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tapering more attractive for RLC lines than for RC lines. For RLC lines, optimum wire tapering achieves a greater reduction in the signal propagation delay as compared to uniform wire sizing. For RLC lines, exponential tapering outperforms uniform repeater insertion. As technology advances, wire tapering becomes more effective than repeater insertion, since a greater reduction in the propagation delay is achieved. Optimum wire tapering achieves a reduction of 36 % in the propagation delay in long RLC interconnect as compared to uniform repeater insertion. Wire tapering can reduce both the propagation delay and power dissipation. Optimum tapering for minimum propagation delay reduces the propagation delay by 15 % and power dissipation by 16 % for an example circuit. The optimum tapering factor to minimize the transient power dissipation of a circuit is described in this paper. An analytic solution to determine the optimum tapering factor that exhibits an error of less than 2 % is provided. Wire tapering is also shown to reduce the power dissipation of a circuit by up to 65%. Wire tapering can also improve signal integrity by reducing the inductive noise of the interconnect lines. Wire tapering reduces the effect of impedance mismatch in digital circuits. The difference between the overshoots and undershoots in the signal waveform of an example clock distribution network is decreased by 34 % as compared to a uniformly sized network producing the same signal characteristics. r 2006 Elsevier B.V. All rights reserved

Transactions Briefs__________________________________________________________________ Exponentially Tapered H-Tree Clock Distribution Networks

Abstract—Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15 % while preservingthe signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasingthe inductive noise. Exponentially tapered interconnects decrease by approximately 35 % the difference between the overshoots in the signal at the input of a tree. As compared to a uniform tree with the same area overhead, overshoots in the signal waveform at the source of the tree are reduced by 40%. Index Terms—Clock distribution network, H-trees, inductive noise, power dissipation, tapered interconnect. I

Optimizing Inductive Interconnect for Low Power

Abstract: The width of an interconnect line affects the total power consumed by a circuit. A trade off exists between the dynamic power and the short-circuit power dissipated in inductive interconnect. The optimum line width that minimizes the total transient power dissipation is determined in this paper. A closed form solution for the optimum width with an error less than 5 % is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 78 % is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined